1. Field of the Invention
The present invention relates to a synchronous circuit system.
2. Description of the Prior Art
In general electronic circuits are designed on an assumption of synchronous operation. For example, two signals .phi..sub.1, .phi..sub.2 present in a circuit must be set to such a fixed relation of timing between them that a logic state change of .phi..sub.1 is regularly in advance of a logic state change of .phi..sub.2.
On the other hand, for asynchronous operation which synchronizes an asynchronous input .phi..sub.2 by a synchronous signal .phi..sub.1, the relationship between their timings is variable or indefinite.
FIG. 1 diagrams a synchronous circuit which transmits .phi..sub.2 synchronously to a contact .circle.A . The relation of timing in the logic state change as between .phi..sub.1 and .phi..sub.2 is predetermined, and thus the signal appearing at contact .circle.A is at an integral "H" level as shown in FIG. 2. On the other hand, owing to an indefinite relation of timing in the logic state change as between .phi..sub.1 and .phi..sub.2, if their logic state changes (falling and rising) to the reverse state at substantially the same timing by chance, then a very short beard-shaped pulse "P" called "glitch or notch" would appear at contact .circle.A because the rising (change to "H" level) of .phi..sub.2 and the falling (change to "L" level) of .phi..sub.1 are offset, as shown in FIG. 3. which may be a cause for erroneous operation of the circuit.
As described above, in one and the same circuit, .phi..sub.2 is used as a synchronous signal as much as possible since the use of .phi..sub.2 as an asynchronous signal cannot assure the normal operation of the circuit under special conditions. For example, the interface part providing the connection between two units, particularly for receiving external signals and performing the control of the circuit operation is liable to get asynchronized. In the prior art, coping with this problem has the technique involved the use of wherein external signals are allowed to be received under certain conditions permitting their logic state change only within a predetermined time period. This however limits the input timing range of external signals.